VLSI Interview Q&A Bank

For a symmetric CMOS inverter (βn = βp), VM = VDD/2. For asymmetric: VM = (Vtn + √(βp/βn)(VDD + Vtp)) / (1 + √(βp/βn)), where Vtn and Vtp are threshold voltages.

Propagation delay tp = (tpHL + tpLH) / 2. tpHL depends on NMOS pull-down strength; tpLH depends on PMOS pull-up strength. Delay ∝ CL × VDD / (I_avg).

Setup time: data must be stable before clock edge. Hold time: data must remain stable after clock edge. Violations cause metastability. Setup slack = arrival time - required time. Hold slack must be > 0.

Clock skew is the difference in clock arrival times at different flip-flops. Positive skew can improve setup timing but worsen hold timing. Negative skew is the opposite. Skew > hold margin causes hold violations.

Slack = Required Arrival Time - Actual Arrival Time. Positive slack = timing met. Negative slack = timing violation. Setup slack = clock period - (data path delay + setup time - clock skew). Hold slack = data path delay - (hold time + clock skew).

Max (setup) analysis: checks that data arrives before the setup window closes. Min (hold) analysis: checks that data does not arrive too early (before hold window opens). Both must pass for correct operation.

OCV accounts for process variations causing different delays on same type of cells. CPPR (Common Path Pessimism Removal) reduces pessimism. AOCV/POCV are advanced OCV models for statistical variation.

Blocking (=): executes sequentially within always block, used for combinational logic. Non-blocking (<=): executes concurrently at end of time step, used for sequential logic (flip-flops). Mixing them incorrectly causes simulation-synthesis mismatch.

Latches are inferred when: (1) not all branches of if-else are covered, (2) case statement is not full or has no default, (3) a signal is not assigned in all conditions. Use complete if-else or case with default to avoid latches in combinational logic.

Latch is level-sensitive: transparent when enable is high, holds when enable is low. Flip-flop is edge-sensitive: captures data only at clock edge. Latches can cause timing issues (long paths) and are generally avoided in synchronous designs.

Netlist → Floorplan → Placement → Clock Tree Synthesis (CTS) → Routing → Timing Closure → DRC/LVS → Tapeout. Each step feeds into the next; timing closure may require multiple iterations.

DRC (Design Rule Check): verifies layout meets foundry manufacturing rules (minimum spacing, width, overlap). LVS (Layout vs Schematic): verifies extracted netlist from layout matches the original schematic/netlist. Both must pass before tapeout.

Pre-characterized collection of basic logic cells (inverter, NAND, NOR, DFF, etc.) at specific process/voltage/temperature corners. Each cell has timing arcs, power models, physical views (LEF, GDS), and functional models (Liberty, Verilog).

Total power = Dynamic power + Static power. Dynamic = α × CL × VDD² × f (switching activity × load cap × voltage squared × frequency). Static = VDD × Ileakage (always present). Dynamic dominates at high frequency; leakage dominates in standby.

Clock gating reduces dynamic power by stopping the clock to idle registers. An AND gate (or ICG - Integrated Clock Gating cell) is inserted before the clock pin. Enable signal controls when the clock propagates. Can save 20-40% of dynamic power.

Scan chain connects all flip-flops in series to allow shift-in of test patterns and shift-out of captured responses. During normal operation, flip-flops operate normally. During test, scan enable overrides to shift data. Enables manufacturing defect detection.

Functional verification uses simulation with testbenches to check RTL behavior. Formal verification uses mathematical proofs (model checking, equivalence checking) to exhaustively prove properties. Formal is complete but has capacity limits; simulation is scalable but coverage-dependent.